1. Field of the Invention
The present invention relates to a novel method and system for optimizing integrated circuit layouts, generally, and particularly, a system and method for modeling performance of a semiconductor device structure for achieving modified ground rules for lithographic feature distances that optimize semiconductor device performance.
2. Description of Prior Art
Lithographic constraints are important factors in determining the efficiency of a circuit layout. In essence, lithographic constraints are conventionally determined by the generally limited capability of a lithographic process to successfully print line features at specified positions within tolerances. A lithographic process involves using a lithographic exposure tool to illuminate a lithographic mask from a range of directions, and focusing a projected image of the mask onto a photosensitive film that coats a partially fabricated integrated circuit on a wafer, such as a silicon wafer. Lithographic process window represents the range of delivered light energy (dose) and image plane defocus within which the projected image adequately represents the desired circuit shapes. After the image is formed, the photosensitive film is developed, and the printed pattern is transferred into a functional process layer in the circuit. The final circuit then consists of many such patterned levels stacked atop one another.
FIG. 1 shows an example portion of a semiconductor device structure 10, e.g., including a FET device such as a pFET, suitable for characterizing a lithographic process impact on device performance. FIG. 1 illustrates a device structure 10 that includes an active device region (RX) 15 formed on a semiconductor substrate that comprises, for example, a polysilicon gate or gate stack (not shown) that separates source and drain regions (not shown).
As shown in FIG. 1, the active device area is characterized as having a width dimension “W”. A conductive wire or line layer (PC) comprising a conductive material, for example, polysilicon (with a silicided top) or metal gate, connects the gate to a landing pad region 25 formed at either side of the active device area 15. The polysilicon line layer (PC) includes an interconnect region 23 having a designed width and landing pad regions 25. Further as shown in FIG. 1 are formed metal contacts 28 for providing electrical contact to the landing pad 25 and, drain and source contact metallurgy 29 for providing electrical contact to the active devices as known in the art. Also shown in FIG. 1 the landing pad 25 is far away form the device active area 15. In the migration to 45 nm CMOS fabrication processes, in order to miniaturize the device, landing pad technology must allow for the shrinking of the feature size of device. However, the spacing between the landing pads has to be decreased so that they can provide enough areas for contact landing as the density of devices in a chip increases. This spacing is represented in FIG. 1 by the arrow labeled “d”. The narrower the spacing, the more difficult it is to fabricate due to the limitations in overlay lithography. The landing pad 25 rounds during lithographic processing and if the distance “d” is small the rounded corner can straddle the device width and influence the device characteristics. In 65 nm technologies the distance “d” is typically large enough that any corner rounding does not come near the device to influence it. However, in 45 nm technologies given the need to increase density, the pads are getting close and d is small enough that the device is being impacted.
The PC landing pad 25 feature of the device structure 10 shown in FIG. 1, is known to influence the device performance. Therefore, it is the case that any compact modeling used needs to account for the device performance effect in the model. That is, the compact model for devices made according to 45 nm fabrication processes needs to account for this device performance effect.
Acceptable tolerances for the printed shapes must yield successful circuit performance, and must also be readily maintained under typical process variations. However, lithographic capability for printing a given feature edge is dependent on other features in the same local region of the circuit layout, as is circuit functionality. Consequently, lithographic constraints should ideally be very dynamic, and potentially incorporate and take advantage of the particular configurational details of large numbers of different local circuit cases.
Generally, however, due to general and practical design reasons, lithographic constraints are usually provided in a highly simplified form, known in the technology as design rules or ground rules, with these rules determining a lithographic capability, in effect, an achievable lithographic process window, which is at least acceptable in the technology, and these rules are normally employed for the entire circuit layout.
Thus, in view of the miniaturization of the device structure shown in FIG. 1, there is a need for a ground rule for landing pad to RX distance “d” at a point where device performance is negatively affected.
Moreover, it would be highly desirable to provide a method and system for more accurately modeling all device performance parametrics by taking into account the impact of lithographic corner rounding effects. Thus, the teachings of the present invention may be used to calculate other device parametrics, e.g., similar to Ion. For instance, the method of the invention may be used to model effects of corner rounding on Idlin, Ioff, Ieff, Gate capacitance, etc. One could also affect the impact of these device performance parametrics through various netlist parameters such as device channel length or threshold voltage (Vt) instead of device width W.